1. Technical Field
The present invention relates to a method and apparatus for data processing in general, and in particular to a method and apparatus for performing result normalization in a floating-point processor. Still more particularly, the present invention relates to a method and apparatus for anticipating leading zeros/ones in a floating-point processor.
2. Description of the Prior Art
Normalization is the removal of leading zeros or leading ones from a respective positive or negative output of a floating-point adder. Full-precision leading-zero anticipators (LZA) (or leading-zero predictors) are commonly utilized to improve the speed of the normalization process. An LZA can be the most critical path of a floating-point adder because it is not obvious a priori whether the result from the adder will be positive or negative. Thus, it is necessary to perform both leading-zero and leading-one analysis, and select the proper normalization shift amount based upon the sign of the result when the result is finally available.
According to the IEEE 754 standard, floating-point numbers are represented by three elements, namely, a binary sign bit, a binary encoded exponent, and a binary encoded mantissa. In a normalized floating-point number, the exponent is that which ensures the first digit of the mantissa is a logical one (except for special cases such as zero, infinities, and unrepresentable numbers). During a normalized floating-point addition, one of the mantissas of the addend and adder is shifted and the exponent is incremented or decremented until the exponents for both the addend and adder are equal. This shifting process is known as alignment. Once aligned, the mantissas of the addend and adder are added or subtracted depending upon the signs of the addend and adder as well as the type of operation (either addition or substraction) to be performed. Once the result (either sum or difference) is formed, depending upon the operation, the sign of the resulting mantissa is examined. If the sign of the result is negative, the boolean complement of the result is initially formed and the sign is then complemented. In order to convert the result to a normalized form, the exponent of the result is decremented and the mantissa of the result is left-shifted until the leading digit of the mantissa is a logical one (in absence of exceptional conditions such as those mentioned supra).
The determination of how many leading zeros or leading ones need to be removed (i.e., the amount of left-shifting) is preferably accomplished in parallel with the arithmetical operations within the floating-point adder. Such concurrency is important because even a few clock cycles may have a major performance impact on the composite speed of the floating-point processor. The present disclosure describes an improved LZA architecture that provides a significant speed improvements over its predecessors.